1. Field of the Invention
The present invention relates generally to a non-volatile electrically erasable semiconductor memory device. More particularly, the invention relates to an over-erase protection scheme for EEPROMs.
2. Description of the Related Art
Recently, personal computers have become popular due to their ability to deliver good computing performance at affordable prices. Although present computers are quite powerful and efficient, there are continuing efforts to increase their performance by increasing speed and lowering costs. One traditional source of time delays in computing systems has been the amount of time required to access auxiliary memory devices. In particular, the magnetic disc auxiliary memory devices are considered quite slow. Therefore, semiconductor memory devices tend to be used as an auxiliary memory device.
Most semiconductor memory devices presently available for use as auxiliary memory devices are DRAMs (SRAMs are seldom used). However, if power is cut off, data stored in a DRAM will be erased. Therefore DRAMs require a backup battery, which is disadvantageous.
Because of the above drawbacks of the most popular auxiliary memory devices, EEPROMs (Electrical Erasable Programmable Read Only Memories), which are electrically programmable, are now being proposed for use as auxiliary semiconductor memory devices. Traditional EEPROMs require two transistors per cell. However, such EEPROMs suffer the drawback of requiring a relatively large area per cell, which in turn results in higher fabrication cost. The use of all-erase (flash-erase) EEPROMs whose cell area is similar in size to ultraviolet-erasable EPROMs (Erasable Programmable Read Only Memories) is being reviewed.
A single transistor EEPROM cell in the form of a tunnel-erase/avalanche-write cell transistor C is shown schematically in FIG. 13. This transistor C has a double-gate structure including a floating gate. As seen in FIG. 14, when data "0" is to be written into such a cell transistor, a high voltage V.sub.pp is applied to both the drain and the control gate while the source is connected to a ground GND. With this arrangement, electrons are injected and a charge accumulates in the floating gate. After the data "0" is written through this operation, the cell transistor C operates as indicated by a characteristic curve D0 shown in FIG. 12. Accordingly, when a 1/0 determination voltage V.sub.0/1 or a cell select signal is applied to the control gate, no current (I.sub.DS) flows between the drain and the source. Thus, the cell transistor C is effectively "off".
As shown in FIG. 13, in order to erase the written data "0", the drain is opened, the control gate is connected to ground GND, and a high voltage V.sub.pp is applied to the source. This removes the charge from the floating gate. The cell transistor C, after the data erase, operates as indicated by a characteristic curve D1 in FIG. 12. Thus, the cell transistor C is turned "on" when the 1/0 determination voltage V.sub.0/1 is applied to the control gate. The condition where a transistor C is turned "on" when subjected to the 1/0 determination value is read as data "1" in that transistor.
An example of a conventional cell array consisting of cell transistors of this type will be explained below referring to FIG. 11. Each row of cell transistors C have their control gates commonly connected to a word line WL.sub.m. For example, a word line WL.sub.1 is commonly connected to the control gates of cell transistors C.sub.11 to C.sub.1j. Each column of multiple cell transistors C have their drains commonly connected to a bit line BL.sub.n. Every cell transistor C has its source connected to ground GND. A voltage V.sub.cc is applied to the bit lines BL.sub.1 to BL.sub.j through load resistors R2.sub.1 to R2.sub.j, for example, in order to steadily set the potentials of the cell transistors depending on whether data is written in the cell transistors.
When one word line and one bit line are selected from among the lines WL.sub.1 to WL.sub.i and BL.sub.1 to BL.sub.j, respectively, a single cell transistor is selected. Specifically, the selected cell is the cell C.sub.mn where the selected work line WL.sub.m and selected bit line BL.sub.n cross each other. If the data "0" is stored in the cell transistor C.sub.mn, the cell transistor C.sub.mn is turned "off" and the selected bit line BL.sub.n becomes a high level. 0n the other hand, if the data "1" is stored in the cell transistor C.sub.mn, the cell transistor C.sub.mn is turned on, and the selected bit line BL.sub.n becomes a low level. The potential of the bit line is then read out as cell information by a sense amplifier.
The drawback of this arrangement is that if too many electrons are removed from the floating gate of a cell transistor C while erasing the data "0", this cell transistor C will be "over-erased". In the over-erased condition, the cell transistor C operates according to a characteristic curve D1.sub.0 as shown in FIG. 12. That is, it now has a negative threshold voltage, and will thus always be in a depletion condition such that it is always effectively "on". When a particular cell transistor C is in an over-erase condition, the potential of the bit line BL connected to that cell transistor C will always be low. Thus, if another cell transistor C connected to the same bit line BL is selected, its cell information cannot be read out, thereby causing a reading failure.
One proposal for overcoming this shortcoming contemplates an erasing method which repeats electrical erasing and data reading until the threshold value of the erased cell transistor becomes a certain value, while checking to insure that the threshold value does not fall negative. However, this method requires a considerable amount of CPU and bus time to control the erasing operations, which undesirably decreases the operation speed of the computer system.